Pipelining: Current Technology - Intel Pentium processor

Intel Pentium

Intel Pentium

The Pentium is a superscalar fully-pipelined microprocessor. A superscalar processor has the ability to process more than one instruction per clock cycle. The Pentium has two execution pipes (U and V) so it is a superscalar level 2 processor.

The Pentium has dual internal caches, for both code and data, and dual TLBs. The TLB is the Translation Lookaside Buffer which caches the virtual page number to the physical page number. This facilitates efficient handling of the pipeline.

The Pentium prefetches as much as 32 bytes of instruction. It employees branch-prediction, a technique that attempts to infer the proper next instruction address, in order to keep the pipeline from stalling.

In the Pentium, a superscalar level 2 processor, two instructions are fetched and decoded simultaneously.
    Instruction pipeline
  1. PF - Fetch and Align instruction
  2. D1 - Decode Instruction, Generate Control Word
  3. D2 - Decode Control Word, Generate memory address
  4. E - Access data cache or Calculate ALU Result
  5. WB - Write Result
    Floating-Point Pipeline
  1. PF - Prefetch
  2. D1 - First Decode
  3. D2 - Second Decode
  4. E - Operand Fetch
  5. X1- First execute
  6. X2 - Second Execute
  7. WF - Write Float
  8. ER - Error Reporting
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Tony Wesley
Comments to author: tony@tonywesley.com
Last Updated: November 27, 1995

URL: http://tonywesley.com/p_5_2.htm