Pipelining: Current Technology - Motorola 68060 processor

Motorola 68000

Motorola 68060

The Motorola 68060 is a fully pipelined superscalar processor. The 68060 allows simultaneous execution of two integer instructions (or 1 integer and 1 float instruction) and one branch during each clock cycle. A branch cache allows most branches to execute in zero cycles. It contains a 4-stage instruction fetch pipeline, and two 6-stage pipelines for the primary operand execution and the secondary operand execution. [TAB95], Ch 12

The 68060 allows simultaneous execution of two integer instructions during one clock cycle.
    IFP (Instruction Fetch Pipeline) stages
  1. IAG - Instruction Address Generation
  2. IC - Instruction cache access
  3. IED - Instruction Early Decode
  4. IB - Instruction Buffer
    OEP (Operand Execution Pipeline) stages
  1. DS - Decode and Select instructions
  2. AG - Address Generation of the operand
  3. OC - Operand Cache access
  4. EX - Execute
  5. DA - Data Available
  6. ST - Store
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Tony Wesley
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Last Updated: November 27, 1995

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