During the design of the Stretch, it appeared that a factor-of-6 improvement in memory speed and a factor-of-10 improvement in basic circuit speed were the best to be achieved. Since the goal was a factor-of-100 overall improvement, the design had to provide for concurrent operation wherever possible [CAM62, p 11,202-6].
Up to eleven successive instructions may be in the registers of the central processing unit at various stages of execution.
The CPU processes and executes instructions with a high degree of overlap of internal functions. Two instruction words, which often are four half-word instructions, and the operands for four more instructions can be simultaneously fetched. At the same time, two more instructions can be decoded and another executed. The CPU is microcoded, with the instruction unit having its own instructions to execute, its own small memory and its own arithmetic unit. This microcoded instruction unit is pipelined as well, with as many of six instructions being in various stages of progress.
By prefetching and examining instructions before execution, it is possible to determine the address of operands required. The look-ahead unit would do this.
Tony Wesley
Comments to author: tony@tonywesley.com
Last Updated: November 26, 1995