Pipelining: Earliest Development

Overlapping Instructions


IBM 700/7000 Series

The IBM 704 computer was a vacumn tube computer that used core memory. It had no overlap in its instruction execution with input/output. The 709 was basically a 704 with some architectural addition. The most important of these was data-synchronizer units (now called channels) which allowed instruction execution and input/output to overlap. This allowed the 709 -- with the same clock cycle as the 704 -- to run about 60% faster. See Table 4.1 .[STA87], [STO75, ch 9]

The IBM 7094 I was a transistor-based machine that still used core memory. This cpu includes an Instruction Backup Register (IBR) which was use to buffer the next instruction. This was used to overlap the execution of one instruction with the fetch of the next. The cycle time was about 6 times faster than the 709 but the system ran about 7.5 times faster than the 709. Hence, this rudimentary pipelining achieved a performance increase in about 25%. Again, see Table 4.1 .

While neither of these gains were tremendous, they pointed the way to continued improvement in performance beyond the increase in circuit speed.


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Tony Wesley
Comments to author: tony@tonywesley.com
Last Updated: November 25, 1995

URL: http://tonywesley.com/p_4_1.htm